EP2SGX60CF780I4N vs EP2SGX60CF780C5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2SGX60CF780I4N sa pamamagitan ng Altera at EP2SGX60CF780C5 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2SGX60CF780I4N | EP2SGX60CF780C5 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix II GX | — |
| Device Type | FPGA | — |
| Logic Elements | 60,440 | 60,440 |
| Logic Blocks / CLBs | 60,440 | — |
| Embedded Memory | 2,542 Kbit (TriMatrix) | — |
| Number of Transceivers | Up to 20 | — |
| Transceiver Data Rate | 622 Mbps to 6.375 Gbps | — |
| Core Supply Voltage | 1.2 V (range 1.15 V to 1.25 V) | — |
| Maximum Internal Frequency | 717 MHz | 717 MHz |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Number of PLLs | 12 (4 fast + 8 enhanced) | — |
| Global Clock Networks | 16 | — |
| Package Type | FC-FBGA-780 (BGA-780) | — |
| Package Size | 23 x 23 mm | — |
| Ball Pitch | 1.0 mm | — |
| Operating Temperature Grade | Industrial | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant | Compliant |
| Device Family | — | Stratix II GX |
| Logic Array Blocks (LABs) | — | 3,022 |
| Embedded Memory Bits | — | 2,544,192 bits |
| Maximum User I/Os | — | 364 |
| Bilang ng Pins | — | 780 |
| Packhaging | — | 780-ball FC-FBGA (29x29 mm, 1 mm pitch) |
| Core Voltage | — | 1.2 V |
| Propagation Delay | — | [DATA_NEEDED: propagation delay in ns] |
| Speed Grade | — | C5 (commercial) |
| Temperature Grade | — | Commercial (0C to +85C) |
| Transceivers | — | Up to 20 multi-gigabit transceivers |
| DSP Blocks | — | Yes (TriMatrix embedded multiplier blocks) |
| PLLs | — | 4 enhanced PLLs + 8 fast PLLs |
| Configuration Schemes | — | Passive Serial, Fast Passive Parallel, JTAG |
| Memory Interfaces | — | DDR/DDR2 SDRAM controllers with source-synchronous PHY |
| Lead-Free | — | Yes |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |