EP2SGX60DF780C5 vs EP2SGX60CF780C5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2SGX60DF780C5 sa pamamagitan ng Intel at EP2SGX60CF780C5 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2SGX60DF780C5 - Stratix II GX FPGA, 60K LEs, 780-FBGA | Intel
EP2SGX60DF780C5 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2SGX60DF780C5 | EP2SGX60CF780C5 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | Stratix II GX | — |
| Logic Elements | 60,440 | 60,440 |
| Logic Array Blocks (LABs) | 3,022 | 3,022 |
| User I/O Pins | 364 | — |
| Packhaging | 780-ball FC-FBGA | 780-ball FC-FBGA (29x29 mm, 1 mm pitch) |
| Package Body Size | 23 x 23 mm | — |
| Ball Pitch | 1.0 mm | — |
| Process Technology | 90 nm | 90 nm CMOS |
| Core Supply Voltage | 1.2 V | — |
| Internal Frequency (max, typical) | ~717 MHz | — |
| Speed Grade | -C5 (commercial, mid-band) | C5 (commercial) |
| Device Type | Field-Programmable Gate Array (FPGA) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | Commercial (0C to +85C) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | Yes |
| Device Family | — | Stratix II GX |
| Embedded Memory Bits | — | 2,544,192 bits |
| Maximum User I/Os | — | 364 |
| Bilang ng Pins | — | 780 |
| Core Voltage | — | 1.2 V |
| Maximum Internal Frequency | — | 717 MHz |
| Propagation Delay | — | [DATA_NEEDED: propagation delay in ns] |
| Temperature Grade | — | Commercial (0C to +85C) |
| Transceivers | — | Up to 20 multi-gigabit transceivers |
| DSP Blocks | — | Yes (TriMatrix embedded multiplier blocks) |
| PLLs | — | 4 enhanced PLLs + 8 fast PLLs |
| Configuration Schemes | — | Passive Serial, Fast Passive Parallel, JTAG |
| Memory Interfaces | — | DDR/DDR2 SDRAM controllers with source-synchronous PHY |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |