EP2SGX90EF1152C3N vs EP2SGX90EF1152C4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2SGX90EF1152C3N sa pamamagitan ng Intel at EP2SGX90EF1152C4 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2SGX90EF1152C3N - Stratix II GX FPGA 90K LE | Intel | 1152-BGA
EP2SGX90EF1152C3N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP2SGX90EF1152C3N | EP2SGX90EF1152C4 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Stratix II GX | — |
| Family | Stratix II GX | Stratix II GX |
| Logic Elements (LE) | 90960 | — |
| Number of LABs/CLBs | 4548 | — |
| Total Memory Bits | 4520448 | — |
| User I/Os | 558 | — |
| Number of Transceivers | [DATA_NEEDED: transceiver count per family] | — |
| Process Technology | 90 nm | 90 nm |
| Core Voltage | 1.2 V | 1.2 V |
| Operating Frequency (max) | 816.9 MHz | — |
| Temperature na Operasyon | 0C to +85C (Commercial) | [DATA_NEEDED: operating temperature] |
| Package Type | FC-FBGA (Flip-Chip Fine-pitch BGA) | FC-FBGA |
| Package Pin Count | 1152 balls | 1152 pins |
| Package Dimensions | 34 mm x 34 mm | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Lead-Free / RoHS | Yes (RoHS compliant) | — |
| Speed Grade | EF | — |
| Temperature Grade | C3 (Commercial) | — |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Logic Cells | — | 90960 cells |
| Logic Array Blocks | — | 4548 LABs |
| User I/O | — | 558 I/O |
| Reported Maximum Frequency | — | 732.1 MHz |
| Alternate Reported Maximum Frequency | — | 717 MHz |
| Alternate Package Description | — | FBGA-1152 |
| Package Mounting | — | Surface Mount |
| Lead-Free Status | — | Lead free |
| Tindminan RoHS | — | RoHS Compliant |
| Transceiver Count | — | [DATA_NEEDED: transceiver count] |
| Configuration Method | — | [DATA_NEEDED: configuration method] |