EP3C40F484C8 vs EP3C40F484C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3C40F484C8 sa pamamagitan ng Intel at EP3C40F484C6N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3C40F484C8 | EP3C40F484C6N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Device Family | Cyclone III | — |
| Logic Elements (LE) | 39,600 | 39,600 |
| Logic Array Blocks (LAB) | 2,475 | — |
| Embedded Memory (bits) | 1,161,216 | — |
| M9K Memory Blocks | 126 | — |
| Embedded 18x18 Multipliers | 56 | 396 |
| PLLs | 4 | 4 |
| Maximum User I/O | 331 | — |
| User I/O Banks | 8 | — |
| Packhaging | 484-ball FBGA (F484), 1.0 mm pitch, 23 x 23 mm | 484-FBGA (F484, 23x23 mm, 1.0 mm pitch) |
| Speed Grade | C8 (commercial, mid-speed) | C6 (commercial, -40C to +125C operating) |
| Temperature na Operasyon | 0C to +85C (commercial) | -40C to +125C |
| Process Node | 60 nm TSMC low-power CMOS | — |
| Supply Voltage (Core) | 1.2 V | — |
| Configuration Scheme | Active serial (AS), Passive serial (PS), JTAG | — |
| Tindminan RoHS | Compliant (lead-free FBGA) | Compliant (lead-free) |
| Level ng MSL | 3 (per JEDEC J-STD-020) | — |
| Family | — | Cyclone III |
| Total Memory Bits | — | 1,161,216 bits |
| User I/O Pins (max) | — | 331 |
| Process Technology | — | 65 nm low-k dielectric |
| Core Voltage | — | 1.2 V |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |
| Configuration Modes | — | JTAG, AS, AP, PS |
| I/O Standards | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL |