EP3C5U256C7 vs EP3C5U256C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3C5U256C7 sa pamamagitan ng Altera at EP3C5U256C6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3C5U256C7 | EP3C5U256C6 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Cyclone III | Cyclone III |
| Logic Elements | 5,136 | 5,136 |
| Total RAM Bits | 423,936 | — |
| Logic Array Blocks (LABs) | 321 | — |
| Embedded Multipliers (18x18) | 46 | 23 |
| Embedded Memory Blocks (M9K) | 23 | — |
| PLLs | 4 | — |
| Maximum User I/O | 182 | 182 |
| Packhaging | 256-UBGA (Ultra FineLine BGA) | 256-UBGA (U256, FineLine BGA) |
| Maximum I/O Pins in Package | 256-LFBGA / 256-UBGA | — |
| Process Technology | 65 nm low-k CMOS | — |
| Speed Grade | -7 (commercial) | 6 (commercial) |
| Temperature ng Junction na Operasyon | 0C to 85C (commercial) | — |
| Supply Voltage - Core (VCCINT) | 1.15 V to 1.25 V | — |
| Supply Voltage - I/O (VCCIO per bank) | 1.2 V to 3.3 V (bank-dependent) | — |
| Configuration Mode | Active Serial (AS), Passive Serial (PS), JTAG | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Tindminan RoHS | Compliant | Lead-free / RoHS compliant |
| Embedded Memory (RAM) | — | 423,936 bits |
| Ball Pitch | — | 1.0 mm |
| Bilang ng Pins | — | 256 |
| General Purpose PLLs | — | 4 |
| Global Clock Networks | — | 10 |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature] |
| Supply Voltage (Core) | — | 1.2 V (typical) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |