EP3C80U484C7 vs EP3CLS70U484C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3C80U484C7 sa pamamagitan ng Intel at EP3CLS70U484C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3C80U484C7 | EP3CLS70U484C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Cyclone III | — |
| Family | EP3C80 | Cyclone III LS |
| Logic Elements | 81,264 | 70,208 |
| Embedded Memory | 2,810,880 bits (295 M9K blocks) | — |
| Embedded 18x18 Multipliers | 244 | — |
| PLLs | 4 | 4 |
| Maximum User I/O Pins | 429 (approximate, package-dependent) | — |
| Packhaging | 484-FBGA (UBGA) | 484-ball UFBGA (U484, 19x19 mm) |
| Speed Grade | -7 (commercial) | 7 |
| Core Voltage | 1.2 V | — |
| I/O Voltage Range | 1.2 V to 3.3 V | — |
| Process Technology | 65 nm low-power CMOS | 65 nm low-power CMOS |
| Temperature ng Junction na Operasyon | 0 C to 85 C (commercial) | — |
| Configuration Modes | Passive Serial, Active Serial, JTAG, AES-encrypted bitstream | — |
| Memory Interface Support | DDR, DDR2, QDRII SDRAM | — |
| I/O Standards | LVDS, LVTTL, LVCMOS, SSTL, HSTL | — |
| Tindminan RoHS | Compliant | Compliant |
| Embedded Memory (bits) | — | 3,068,928 |
| User I/O Count | — | 278 |
| Core Supply Voltage | — | 1.2 V |
| Maximum Internal Frequency | — | 437.5 MHz |
| Multipliers (18x18) | — | [DATA_NEEDED: 18x18 multiplier count] |
| Global Clock Networks | — | 20 |
| Configuration Schemes | — | AS, PS, JTAG, FPP |
| Temperature na Operasyon | — | 0C to +85C (commercial, C7 speed grade) |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |
| Level ng MSL | — | 3 |