EP3CLS100F484I7 vs EP3CLS100F484I7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3CLS100F484I7 sa pamamagitan ng Intel at EP3CLS100F484I7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3CLS100F484I7 | EP3CLS100F484I7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Device Family | Cyclone III LS | — |
| Logic Elements (LE) | 100,448 | 100,448 |
| Logic Array Blocks (LABs) | 278 | — |
| Total Embedded Memory Bits | 4,451,328 bits | — |
| Embedded Memory (M9K Blocks) | 610 (per datasheet family) | — |
| DSP Blocks (18x18 Multipliers) | 66 | — |
| 18x18 Hardware Multipliers | 16 dedicated | — |
| PLLs | 4 | 4 |
| Maximum User I/Os | 429 | — |
| Packhaging | 484-ball FBGA (FineLine BGA) | 484-ball FBGA (F484) |
| Core Supply Voltage | 1.2 V | — |
| I/O Standards Supported | LVDS, LVCMOS, LVTTL, SSTL, HSTL | — |
| Hanay ng Temperature na Operasyon | -40C to +85C (Industrial) | — |
| Process Technology | TSMC 65 nm low-power (LP) | 65 nm CMOS |
| Configuration Method | Serial/Parallel, AES-256 encrypted (LS feature) | — |
| External Memory Support | DDR, DDR2, QDRII, RLDRAM II | — |
| Tindminan RoHS | Compliant | — |
| Family | — | Cyclone III LS |
| Device Type | — | FPGA - Field Programmable Gate Array |
| Logic Array Blocks (LAB) | — | 6,278 |
| Embedded Memory | — | 4,451,328 bits (M9K blocks) |
| 18x18 Multipliers | — | 278 |
| User I/O Pins (max) | — | 294 |
| Core Supply Voltage (VCCINT) | — | 1.2 V |
| Maximum Internal Frequency | — | 437.5 MHz |
| Operating Temperature (Industrial) | — | -40 °C to +100 °C |
| Speed Grade | — | 7 (medium) |
| Configuration Modes | — | AS, PS, JTAG, FPP |
| Lead-Free / RoHS | — | Yes (LEAD FREE per FindIC) |