EP3CLS100U484C7N vs EP3CLS100U484I7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3CLS100U484C7N sa pamamagitan ng Altera at EP3CLS100U484I7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP3CLS100U484C7N - Cyclone III LS FPGA, 100K LE, 484-FBGA | Altera
EP3CLS100U484C7N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP3CLS100U484C7N | EP3CLS100U484I7N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Device Family | Cyclone III LS | Cyclone III LS |
| Logic Elements | 100,448 | — |
| Embedded Memory | 4,451,328 bits (4.4 Mbit) | 432 M9K blocks (9 Kbit each) |
| User I/O Pins | 278 | — |
| Packhaging | 484-ball FBGA (UBGA) | 484-FBGA (UBGA) |
| Process Technology | 65 nm TSMC low-power | TSMC 65 nm low-power (LP) |
| Core Supply Voltage | 1.2 V | 1.2 V |
| Speed Grade | 7 (commercial) | — |
| Maximum Internal Frequency | 437.5 MHz | — |
| Temperature na Operasyon | 0C to +85C (commercial) | -40C to +100C (Industrial, 'I') |
| Configuration Mode | AS / AP / PS / JTAG | — |
| DSP Blocks (18x18 multipliers) | [DATA_NEEDED: DSP block count] | — |
| PLLs | [DATA_NEEDED: PLL count] | 4 |
| I/O Banks | 8 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Tindminan RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| Series | — | Cyclone III |
| Logic Elements (LE) | — | 100,448 |
| Total RAM Bits | — | 4,451,328 bits (~4.4 Mbit) |
| Maximum User I/O | — | 278 |
| Number of LABs | — | 6,278 |
| DSP Blocks | — | 24 (18x18 multipliers) |
| I/O Supply Voltage | — | 1.2 V to 3.3 V (per bank) |
| Security Features | — | AES-128 bit-stream encryption, JTAG disable, tamper detection |
| Level ng MSL | — | 3 (168 hours) |