EP3CLS200F484C7N vs EP3CLS200F484C8ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3CLS200F484C7N sa pamamagitan ng Intel at EP3CLS200F484C8ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP3CLS200F484C8ES - Cyclone III LS FPGA, 198K LE, 484-BGA | Altera
EP3CLS200F484C8ES ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP3CLS200F484C7N | EP3CLS200F484C8ES |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Cyclone III LS | — |
| Logic Elements (LE) | 198,464 | 198,464 |
| Logic Array Blocks (LAB) | 12,404 | — |
| Embedded Memory | 8,211,456 bits | 4,488 Kbit (M9K blocks) |
| Embedded 18x18 Multipliers | 210 | — |
| User I/O | 226 | — |
| Packhaging | 484-ball FBGA (FineLine BGA, 23x23 mm) | 484-ball FBGA (FineLine BGA) |
| Core Voltage | 1.2 V | — |
| Temperature na Operasyon | 0C to +85C (commercial) | — |
| Process Technology | 65 nm low-power CMOS | 65 nm |
| Configuration Modes | AS, PS, JTAG (IEEE 1149.1) | — |
| I/O Standards | LVDS, LVTTL, LVCMOS, SSTL, HSTL | — |
| Number of I/O Banks | 8 | — |
| Hot Socketing | Supported | — |
| PLLs | 4 | 4 |
| Tindminan RoHS | Compliant | Compliant |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Device Family | — | Cyclone III LS |
| Logic Cells / Logic Blocks | — | 47 |
| Maximum User I/O | — | 210 |
| Core Supply Voltage | — | 1.2 V |
| Fabric Performance | — | 402 MHz (max) |
| Operating Temperature Grade | — | Commercial (C) |
| Speed Grade | — | 8 |
| On-Chip Termination (OCT) | — | Supported |
| I/O Standards Supported | — | LVDS, LVCMOS, SSTL, HSTL (per datasheet) |