EP3CLS70F484I7N vs EP3CLS150F484I7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3CLS70F484I7N sa pamamagitan ng Intel at EP3CLS150F484I7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3CLS70F484I7N - Cyclone III LS FPGA, 70K LEs, 484-FBGA | Intel
EP3CLS70F484I7N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP3CLS70F484I7N | EP3CLS150F484I7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Family | Cyclone III LS | Cyclone III LS |
| Logic Elements (LEs) | 70,208 | — |
| Embedded Memory Bits | 3,068,928 bits | — |
| User I/Os | 278 | — |
| DSP Blocks (18x18 Multipliers) | 274 | — |
| PLLs | 4 | 4 |
| Maximum User I/O Pins | 294 | — |
| Process Technology | 65 nm low-power CMOS | 65 nm low-power CMOS |
| Core Supply Voltage | 1.2 V | — |
| Packhaging | 484-ball FBGA (FineLine BGA), 1.0 mm pitch | FBGA-484 (FineLine BGA) |
| Temperature na Operasyon | -40C to +100C (Industrial, I7 speed grade) | -40C to +100C (Industrial, 'I') |
| Configuration Mode | Passive Serial, Active Serial, JTAG | — |
| Memory Interfaces | DDR2, DDR3, QDRII+, RLDRAM II | — |
| LVDS Data Rate | Up to 875 Mbps per channel | — |
| Tindminan RoHS | Compliant | — |
| Logic Elements | — | 150,848 |
| Logic Array Blocks (LABs) | — | 9,428 |
| Embedded Memory (M9K blocks) | — | 6,137,856 bits (6.14 Mbit) |
| Embedded Multipliers (18x18) | — | 210 |
| Global Clock Networks | — | 20 |
| Maximum User I/O | — | 210 |
| Core Voltage | — | 1.0 V (typical) |
| Speed Grade | — | 7 |
| Lead-Free / RoHS | — | Yes (suffix 'N') |
| Configuration Schemes | — | AS, AP, PS, FPP, JTAG |
| Security Features | — | 256-bit AES bitstream encryption, JTAG secure mode, CRC |
| DSP Performance | — | Up to 450 MHz on 18x18 multipliers |