EP3SE110F1152C4LN vs EP3SE110F1152C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE110F1152C4LN sa pamamagitan ng Intel at EP3SE110F1152C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SE110F1152C3N - Stratix III E FPGA, 107.5K LE, FC-FBGA-1152 | Intel
EP3SE110F1152C3N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP3SE110F1152C4LN | EP3SE110F1152C3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Huling Pagbili |
| Family | Stratix III E (Enhanced logic) | Stratix III E |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements (LE) | 107,500 | 107,500 |
| Logic Array Blocks (LAB) | 4,300 | — |
| Adaptive Logic Modules (ALM) | Yes | — |
| Embedded Memory (bits) | 8,936,448 | — |
| Maximum User I/O | 744 | — |
| Maximum Internal Clock Frequency | 717 MHz | — |
| Process Technology | 65 nm | 65 nm TSMC |
| Core Supply Voltage (VCCINT) | 0.9 V nominal (0.86 V to 0.94 V) | — |
| Temperature na Operasyon | 0 C to 85 C (commercial) | 0 °C to 85 °C (commercial) |
| Packhaging | 1152-pin FC-FBGA (BBGA) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Configuration Method | JTAG / serial / parallel flash | — |
| Tindminan RoHS | Compliant | — |
| Series | — | Stratix III |
| Logic Array Blocks (LABs) | — | 4,300 |
| Total RAM Bits | — | 8,936,448 |
| User I/Os | — | 744 |
| Operating Frequency (max) | — | 500 MHz |
| Core Supply Voltage | — | 1.1 V nominal |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O supply range] |
| Package Type | — | FC-FBGA-1152 (flip-chip BGA) |
| Speed Grade | — | C3 |
| Style ng Pagpapasok | — | SMD/SMT (Tray) |
| DSP Blocks | — | Yes (embedded multipliers) |
| Uri ng Memory | — | M9K and M144K block RAM |
| External Memory Support | — | DDR/DDR2/DDR3 with read/write leveling |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| RoHS | — | [DATA_NEEDED: RoHS status] |
| Lead-Free | — | Yes (per Altera/Intel datasheet family convention) |