EP3SE110F1152C4N vs EP3SE110F1152I2N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE110F1152C4N sa pamamagitan ng Intel at EP3SE110F1152I2N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SE110F1152C4N - Stratix III E FPGA, 107.5K LE, 1152-FCBGA | Intel
EP3SE110F1152C4N ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP3SE110F1152C4N | EP3SE110F1152I2N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Family | Stratix III Enhanced (E) | Stratix III |
| Logic Elements | 107,500 | — |
| Memory Bits | 8,936,448 | — |
| Embedded Multipliers (18x18) | 896 | — |
| Logic Array Blocks (LABs) | 4300 | — |
| User I/O Pins | 744 | 744 |
| Core Voltage | 1.1 V | — |
| Process Technology | 65 nm | 40 nm low-power CMOS |
| Maximum Operating Frequency | 450 MHz | — |
| Packhaging | 1152-ball FCBGA (Flip-Chip BGA) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +85C (Commercial) | -40C to +100C (industrial) |
| Configuration Method | Passive Serial / Fast Passive Parallel / JTAG / AES-256 | — |
| Tindminan RoHS | Compliant | — |
| Level ng MSL | 3 (168 hours) | — |
| Design Software | Quartus II (v9.1 or later) | — |
| Series | — | Stratix III Enhanced (EP3SE110) |
| Logic Elements (LE) | — | 107,500 |
| Logic Array Blocks (LABs) / CLBs | — | 4,300 |
| System Gates | — | 8,936,448 |
| Number of Terminals | — | 1,152 |
| Package Code | — | BGA (FCBGA) |
| Package Shape | — | Square |
| Ball Pitch | — | 1.00 mm |
| Supply Voltage Range | — | 1.05 V to 1.15 V (nominal 1.1 V) |
| Maximum Internal Clock Frequency | — | 100 MHz (per distributor summary; device supports multi-Gbps transceivers) |
| Speed Grade | — | I2 |
| Lead-Free / RoHS | — | Yes (suffix N) |