EP3SE110F1152I3N vs EP3SE110F1152C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE110F1152I3N sa pamamagitan ng Altera at EP3SE110F1152C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP3SE110F1152I3N - Stratix III E FPGA, 107K LE, 1152-FCBGA | Altera
EP3SE110F1152I3N ⚠ Huling PagbiliIntel
EP3SE110F1152C4N - Stratix III E FPGA, 107.5K LE, 1152-FCBGA | Intel
EP3SE110F1152C4N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP3SE110F1152I3N | EP3SE110F1152C4N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Huling Pagbili |
| Series | Stratix III E | — |
| Family | Stratix III E FPGA | Stratix III Enhanced (E) |
| Manufacturer | Altera (now Intel PSG) | — |
| Logic Elements (LE) | 107,500 | — |
| Total RAM Bits | 8,936,448 | — |
| Maximum User I/Os | 744 | — |
| Logic Array Blocks (LABs) | 4300 | 4300 |
| Number of I/O Banks | Modular I/O banks (see Stratix III Device Handbook) | — |
| Core Voltage | 1.1 V | 1.1 V |
| Process Technology | 65 nm CMOS | 65 nm |
| Hanay ng Temperature na Operasyon | -40C to +100C (industrial, I3 grade) | — |
| Speed Grade | -3 (I3 fast grade, industrial) | — |
| Packhaging | 1152-ball FC-FBGA (Flip-Chip Fine-pitch BGA) | 1152-ball FCBGA (Flip-Chip BGA) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead-Free / RoHS | Lead-free (N suffix); RoHS compliance status: see Stratix III Device Handbook | — |
| Configuration | JTAG via Quartus II; supports AS, PS, JTAG, FPP modes | — |
| Internal Supply Voltage (Max) | 0.94 V (per Partstack listing) | — |
| Logic Elements | — | 107,500 |
| Memory Bits | — | 8,936,448 |
| Embedded Multipliers (18x18) | — | 896 |
| User I/O Pins | — | 744 |
| Maximum Operating Frequency | — | 450 MHz |
| Temperature na Operasyon | — | 0C to +85C (Commercial) |
| Configuration Method | — | Passive Serial / Fast Passive Parallel / JTAG / AES-256 |
| Tindminan RoHS | — | Compliant |
| Level ng MSL | — | 3 (168 hours) |
| Design Software | — | Quartus II (v9.1 or later) |