EP3SE260H780C3N vs EP3SE260H780C2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE260H780C3N sa pamamagitan ng Intel at EP3SE260H780C2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EP3SE260H780C2 EP3SE260H780C2 - Stratix III E 260K LE FPGA | Altera | 780-BGA

EP3SE260H780C2 - Stratix III E 260K LE FPGA | Altera | 780-BGA

EP3SE260H780C2 ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP3SE260H780C3N EP3SE260H780C2
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Huling Pagbili
Series Stratix® III E Stratix III
Logic Elements (LE) 255,000 255,000
Embedded Memory (bits) 16,672,768 16,672,768
Number of LABs/CLBs 10,200 10,200
User I/Os 488 488
Number of Pins / Balls 780 —
Packhaging 780-BBGA, FCBGA (H780) 780-BBGA, FCBGA
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon 0 °C to +85 °C (C grade, commercial) 0C to +85C (Commercial)
Process Technology 40 nm CMOS —
Maximum Core Frequency [DATA_NEEDED: maximum core frequency MHz] —
Supply Voltage (VCCINT) [DATA_NEEDED: VCCINT nominal V] —
Transceivers [DATA_NEEDED: number of embedded transceivers and max data rate] —
DSP Blocks [DATA_NEEDED: number of DSP blocks and precision] —
Tindminan RoHS Compliant (lead-free 'N' suffix) Compliant
Level ng Sensitivity sa Asid ng Moisture (MSL) [DATA_NEEDED: MSL level per JEDEC J-STD-020] —
Configuration Method SRAM-based, configured via JTAG / passive / active serial / fast passive parallel —
Design Toolchain Altera Quartus II (legacy); Intel Quartus Prime —
Family — Stratix® III E
Adaptive Logic Modules (ALM) — 102,000
Process Node — 65 nm
Core Voltage — 0.86 V to 1.15 V
Lead Free — Yes
Level ng MSL — 3 (per JEDEC J-STD-020)

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita