EP3SE50F780C4LN vs EP3SE50F780C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE50F780C4LN sa pamamagitan ng Intel at EP3SE50F780C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3SE50F780C4LN | EP3SE50F780C4N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Family | Stratix III E | Stratix III E |
| Logic Elements | 47,500 | — |
| LABs (Logic Array Blocks) | 1,900 | — |
| Embedded Memory | 5,760,000 bits | — |
| User I/Os | 488 | — |
| Packhaging | 780-ball FC-FBGA | 780-Ball FBGA, 29 mm x 29 mm, 1.0 mm pitch |
| Process Node | 65 nm | 40 nm |
| Core Voltage | 0.9 V | — |
| Speed Grade | C4 | — |
| Temperature na Operasyon | 0°C to 85°C (Commercial) | 0C to +85C (C4 commercial grade) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Lead-Free / RoHS | Yes (L suffix) | — |
| Maximum Toggle Frequency | 375 MHz | — |
| Configuration Modes | Passive Serial, Fast Passive, Active Serial (AS), Active Parallel (AP), JTAG | JTAG, Passive Serial, Fast Passive Parallel |
| DSP Blocks | Yes (embedded multipliers) | — |
| Block RAM Type | M9K + M144K | — |
| Memory Architecture | SRAM-based, reprogrammable | — |
| Tindminan RoHS | Compliant | Lead-free / RoHS compliant |
| Logic Elements (LE) | — | 47,500 |
| Embedded Memory Bits | — | 5,760,000 |
| Embedded Memory (M9K/M144K blocks) | — | 488 (per family datasheet) |
| Number of LABs | — | 1900 |
| Maximum User I/Os | — | 488 |
| DSP Blocks (18x18 multipliers) | — | 432 |
| PLLs | — | 12 (per family datasheet) |
| Maximum Operating Frequency | — | 717 MHz |
| Transceiver Channels | — | Up to 12 (per family, model-dependent) |
| Transceiver Data Rate | — | Up to 6.375 Gbps (per Stratix III E family) |
| Volte ng Pagbibigay | — | Core 0.9 V, I/O 1.2 V-3.3 V (multi-rail) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020, FBGA package) |
| Hard Memory Controller | — | DDR2/DDR3 SDRAM (per Stratix III E family) |