EP3SL110F1152I3N vs EP3SL110F1152C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL110F1152I3N sa pamamagitan ng Altera at EP3SL110F1152C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP3SL110F1152I3N - Stratix III L FPGA, 107.5K LE, 1152-BGA | Altera
EP3SL110F1152I3N ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP3SL110F1152I3N | EP3SL110F1152C4N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | Stratix III L | Stratix III |
| Logic Elements | 107,500 | — |
| Logic Array Blocks (LABs) | 4,300 | — |
| User I/Os | 744 | — |
| Embedded Memory Bits | 4,992,000 | 4992000 |
| Process Technology | 65 nm | 65 nm TSMC low-power CMOS |
| Core Voltage | 1.1 V | — |
| Maximum Operating Frequency | 500 MHz | — |
| Packhaging | 1152-ball FC-FBGA | 1152-BBGA, FCBGA |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40C to +100C (Industrial) | 0C to +85C (Commercial) |
| Configuration Interface | JTAG, Passive Serial, Fast Passive Parallel | — |
| Speed Grade | I3 | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Level ng MSL | [DATA_NEEDED: MSL level] | 3 (168 hours) |
| Series | — | Stratix III L |
| Logic Elements (LE) | — | 107500 |
| Maximum User I/O | — | 744 |
| DSP Blocks | — | 432 |
| PLLs | — | 12 |
| Transceivers | — | 12 (3.125 Gbps) |
| I/O Banks | — | 24 |
| Ball Pitch | — | 1.0 mm |
| Lead-Free | — | Yes |