EP3SL200H780C3N vs EP3SL200H780I3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL200H780C3N sa pamamagitan ng Intel at EP3SL200H780I3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3SL200H780C3N | EP3SL200H780I3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | Stratix III L (low-power) | Stratix III L |
| Process Node | 40 nm | 40 nm |
| Logic Elements | 200,000 | 200,000 |
| Embedded Memory Bits | 10,901,504 bits | — |
| Logic Array Blocks (LABs) | 8,000 | — |
| User I/Os | 488 | — |
| Packhaging | 780-Ball FCBGA (HBGA), 29 x 29 mm | 780-BBGA, FCBGA |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Maximum Internal Clock Frequency | 800 MHz | — |
| Transceivers | 24 channels, up to 3.75 Gbps | — |
| DSP Blocks | 384 | — |
| Speed Grade | C3 (commercial, -3 speed) | — |
| Temperature na Operasyon | 0C to +85C (commercial) | -40C to +100C (Industrial) |
| Voltage - Core | 0.9 V / 1.0 V (core, VCC) | — |
| Voltage - I/O | 1.2 V to 3.3 V (VCCIO banks) | — |
| Level ng MSL | 3 | — |
| Lead-Free / RoHS | Yes | — |
| Mounting Pitch | 1.0 mm ball pitch | — |
| PLLs | 12 (Stratix III PLL array) | — |
| Configuration | JTAG IEEE Std 1149.1, passive/active serial | — |
| RAM Bits | — | 10,901,504 |
| User I/O | — | 488 |
| Package Pin Count | — | 780 |
| Supply Voltage (Core) | — | 0.9 V |
| Technology | — | CMOS, 40 nm |
| Number of Terminals | — | 780 |
| Case / Package Code | — | BGA-780 |
| Tindminan RoHS | — | Compliant |
| Lead-Free | — | Yes |