EP3SL340F1517I4 vs EP3SL340F1517I4L Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL340F1517I4 sa pamamagitan ng Altera at EP3SL340F1517I4L sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP3SL340F1517I4 - Stratix III L FPGA, 337.5K LE, 1517-FBGA | Altera
EP3SL340F1517I4 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP3SL340F1517I4 | EP3SL340F1517I4L |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Series | Stratix III L | — |
| Manufacturer | Altera (now Intel PSG) | — |
| Logic Elements (LE) | 337,500 | — |
| Embedded Memory Bits | 18,822,144 (approx. 2.25 Mbyte) | — |
| Maximum User I/O | 976 | — |
| LAB/CLB Count | 13,500 | — |
| Process Node | 40 nm | 65 nm CMOS (TSMC) |
| Packhaging | 1517-BBGA, FCBGA (Flip-Chip BGA) | 1517-ball FBGA (FCBGA), 40 x 40 mm |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature na Operasyon | -40 C to +100 C (Industrial) | — |
| Speed Grade | 4 | I4L (industrial, low-power) |
| Supply Voltage Core | [DATA_NEEDED: VCCINT nominal] | — |
| Maksimum na Taktiko ng Oras | 717 MHz | — |
| Tindminan RoHS | [DATA_NEEDED] | Compliant |
| Level ng MSL | [DATA_NEEDED: JEDEC moisture sensitivity level] | — |
| Family | — | Stratix III L |
| Core Logic Elements | — | 337,500 |
| Embedded Memory (bits) | — | 18,822,144 |
| Logic Array Blocks (LABs) | — | 13,500 |
| Maximum User I/Os | — | 976 |
| Maximum Core Frequency | — | 717 MHz |
| DSP Blocks (18x18 multipliers) | — | 576 |
| PLLs | — | 4 |
| Transceivers | — | 24 channels, up to 6.375 Gbps |
| Operating Temperature (Junction) | — | -40C to +100C |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | 4 |
| Supply Voltage (Core) | — | [DATA_NEEDED: core voltage value] |
| External Memory Interfaces | — | DDR3, DDR2, QDR II+, RLDRAM II |
| Configuration | — | FPGA (SRAM-based, volatile) |