EP3SL50F484C2N vs EP3SL50F484C2G Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL50F484C2N sa pamamagitan ng Altera at EP3SL50F484C2G sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP3SL50F484C2N - Stratix III L FPGA, 47.5K LE, 484-FBGA | Altera
EP3SL50F484C2N ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP3SL50F484C2N | EP3SL50F484C2G |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Series | Stratix III L | — |
| Family | Stratix III | Stratix III L |
| Logic Elements | 47,500 | 47,500 LE |
| Logic Array Blocks (LABs) | 1,900 | — |
| Embedded Memory | 2,184,192 bits | 2,184,192 bits (2.08 Mbit) |
| User I/Os | 296 | — |
| Operating Frequency | 600 MHz | — |
| Process Technology | 65 nm | 65 nm CMOS |
| Core Supply Voltage | 1.1 V | — |
| Packhaging | 484-ball FC-FBGA (Flip-Chip) | 484-ball FCBGA (FBGA-484) |
| Package Code | BGA | — |
| Package Shape | Square | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature Grade | Industrial (C2) | — |
| Lead-Free / RoHS | Yes (compliant) | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Configuration Method | JTAG / Passive Serial / FPP | — |
| Adaptive Logic Modules (ALMs) | — | 19,000 ALM |
| Maximum User I/Os | — | 296 I/O |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| Operating Supply Voltage (Core) | — | 1.1 V |
| Maximum Operating Temperature | — | +85 C |
| Minimum Operating Temperature | — | 0 C |
| Maksimum na Taktiko ng Oras | — | 600 MHz |
| Style ng Pagpapasok | — | SMD/SMT |
| Packaging | — | Tray |
| Tindminan RoHS | — | Compliant |
| Total Transceivers | — | [DATA_NEEDED: transceiver count] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |