EP3SL50F484C3 vs EP3SL50F484C4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL50F484C3 sa pamamagitan ng Intel at EP3SL50F484C4 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP3SL50F484C4 - Stratix III L FPGA, 47.5K LE, 484-FBGA | Altera
EP3SL50F484C4 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP3SL50F484C3 | EP3SL50F484C4 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Huling Pagbili |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Family | Stratix III L | Stratix III L |
| Logic Cells | 47,500 cells | — |
| Technology | 65 nm | — |
| Listed Frequency | 500 MHz | — |
| Internal Frequency | 800 MHz | — |
| Volte ng Pagbibigay | 1.1 V | — |
| Logic Array Blocks | 1,900 LABs | — |
| User I/O | 296 I/Os | — |
| Packhaging | 484-pin FC-FBGA | 484-Ball FBGA |
| Bilang ng Pin | 484 pins | — |
| Package Type | FBGA-484 | — |
| Temperature na Operasyon | 0 °C to 85 °C | 0C to 85C (Commercial) |
| Device Category | Programmable logic IC | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Manufacturer Technology Description | 65-nm low-power high-performance FPGA | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Configuration Memory | [DATA_NEEDED: configuration memory size] | — |
| Embedded Transceivers | [DATA_NEEDED: embedded transceiver count] | — |
| Power Consumption | [DATA_NEEDED: power consumption] | — |
| Logic Elements | — | 47,500 |
| Embedded Memory Bits | — | 2,184,192 |
| Logic Array Blocks (LABs) | — | 1,900 |
| User I/Os | — | 296 |
| Ball Pitch | — | 1.0 mm |
| Core Voltage | — | 1.1 V |
| Process Technology | — | 65 nm CMOS |
| Maximum Internal Frequency | — | 717 MHz |
| DSP Blocks | — | Yes (variable count) |
| Hard Memory Controllers | — | Yes |