EP3SL50F484C4L vs EP3SL50F484C2N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL50F484C4L sa pamamagitan ng Intel at EP3SL50F484C2N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP3SL50F484C2N - Stratix III L FPGA, 47.5K LE, 484-FBGA | Altera
EP3SL50F484C2N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP3SL50F484C4L | EP3SL50F484C2N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obs | Huling Pagbili |
| Family | Stratix III L | Stratix III |
| Logic Elements (LE) | 47,500 | — |
| Logic Array Blocks (LABs) | 1,900 | 1,900 |
| User I/O Count | 296 | — |
| Total RAM Bits | 2,184,192 | — |
| Core Voltage | 0.9 V | — |
| Process Technology | 65 nm CMOS | 65 nm |
| Hanay ng Temperature na Operasyon | 0°C to 85°C (commercial) | — |
| Packhaging | 484-ball FBGA (FineLine BGA) | 484-ball FC-FBGA (Flip-Chip) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Maximum Fabric Frequency | [DATA_NEEDED: maximum fabric frequency] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| Transceivers | [DATA_NEEDED: number of transceivers] | — |
| Level ng MSL | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL level] |
| Tindminan RoHS | Compliant | — |
| Design Software | Quartus II | — |
| Architecture | Adaptive Logic Module (ALM) | — |
| Series | — | Stratix III L |
| Logic Elements | — | 47,500 |
| Embedded Memory | — | 2,184,192 bits |
| User I/Os | — | 296 |
| Operating Frequency | — | 600 MHz |
| Core Supply Voltage | — | 1.1 V |
| Package Code | — | BGA |
| Package Shape | — | Square |
| Temperature Grade | — | Industrial (C2) |
| Lead-Free / RoHS | — | Yes (compliant) |
| Configuration Method | — | JTAG / Passive Serial / FPP |