EP3SL50F484C4L vs EP3SL50F484C4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL50F484C4L sa pamamagitan ng Intel at EP3SL50F484C4 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP3SL50F484C4 - Stratix III L FPGA, 47.5K LE, 484-FBGA | Altera
EP3SL50F484C4 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP3SL50F484C4L | EP3SL50F484C4 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obs | Huling Pagbili |
| Family | Stratix III L | Stratix III L |
| Logic Elements (LE) | 47,500 | — |
| Logic Array Blocks (LABs) | 1,900 | 1,900 |
| User I/O Count | 296 | — |
| Total RAM Bits | 2,184,192 | — |
| Core Voltage | 0.9 V | 1.1 V |
| Process Technology | 65 nm CMOS | 65 nm CMOS |
| Hanay ng Temperature na Operasyon | 0°C to 85°C (commercial) | — |
| Packhaging | 484-ball FBGA (FineLine BGA) | 484-Ball FBGA |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Maximum Fabric Frequency | [DATA_NEEDED: maximum fabric frequency] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | Yes (variable count) |
| Transceivers | [DATA_NEEDED: number of transceivers] | — |
| Level ng MSL | 3 (per JEDEC J-STD-020) | — |
| Tindminan RoHS | Compliant | Compliant |
| Design Software | Quartus II | — |
| Architecture | Adaptive Logic Module (ALM) | — |
| Logic Elements | — | 47,500 |
| Embedded Memory Bits | — | 2,184,192 |
| User I/Os | — | 296 |
| Ball Pitch | — | 1.0 mm |
| Temperature na Operasyon | — | 0C to 85C (Commercial) |
| Maximum Internal Frequency | — | 717 MHz |
| Hard Memory Controllers | — | Yes |