EP3SL50F484C4L vs EP3SL50F484C4LN Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL50F484C4L sa pamamagitan ng Intel at EP3SL50F484C4LN sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3SL50F484C4L | EP3SL50F484C4LN |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obs | NRND |
| Family | Stratix III L | Stratix III L |
| Logic Elements (LE) | 47,500 | — |
| Logic Array Blocks (LABs) | 1,900 | 1,900 |
| User I/O Count | 296 | — |
| Total RAM Bits | 2,184,192 | — |
| Core Voltage | 0.9 V | — |
| Process Technology | 65 nm CMOS | — |
| Hanay ng Temperature na Operasyon | 0°C to 85°C (commercial) | — |
| Packhaging | 484-ball FBGA (FineLine BGA) | 484-ball FBGA (FCBGA) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Maximum Fabric Frequency | [DATA_NEEDED: maximum fabric frequency] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | [DATA_NEEDED: DSP block count] |
| Transceivers | [DATA_NEEDED: number of transceivers] | [DATA_NEEDED: transceiver count and data rate] |
| Level ng MSL | 3 (per JEDEC J-STD-020) | — |
| Tindminan RoHS | Compliant | Compliant |
| Design Software | Quartus II | — |
| Architecture | Adaptive Logic Module (ALM) | — |
| Logic Elements | — | 47,500 |
| Embedded Memory | — | 2,184,192 bits |
| User I/O Pins | — | 296 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Speed Grade | — | -4 |
| Temperature Grade | — | Commercial (0C to +85C) |
| Process Node | — | 65 nm |
| PLLs | — | [DATA_NEEDED: PLL count] |
| Operating Voltage | — | [DATA_NEEDED: VCCINT and VCCIO] |