EP3SL50F484C4LN vs EP3SL50F484C2N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL50F484C4LN sa pamamagitan ng Intel at EP3SL50F484C2N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP3SL50F484C2N - Stratix III L FPGA, 47.5K LE, 484-FBGA | Altera
EP3SL50F484C2N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP3SL50F484C4LN | EP3SL50F484C2N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Family | Stratix III L | Stratix III |
| Logic Elements | 47,500 | 47,500 |
| Logic Array Blocks (LABs) | 1,900 | 1,900 |
| Embedded Memory | 2,184,192 bits | 2,184,192 bits |
| User I/O Pins | 296 | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Packhaging | 484-ball FBGA (FCBGA) | 484-ball FC-FBGA (Flip-Chip) |
| Speed Grade | -4 | — |
| Temperature Grade | Commercial (0C to +85C) | Industrial (C2) |
| Process Node | 65 nm | — |
| Transceivers | [DATA_NEEDED: transceiver count and data rate] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| PLLs | [DATA_NEEDED: PLL count] | — |
| Operating Voltage | [DATA_NEEDED: VCCINT and VCCIO] | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant | — |
| Series | — | Stratix III L |
| User I/Os | — | 296 |
| Operating Frequency | — | 600 MHz |
| Process Technology | — | 65 nm |
| Core Supply Voltage | — | 1.1 V |
| Package Code | — | BGA |
| Package Shape | — | Square |
| Lead-Free / RoHS | — | Yes (compliant) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Configuration Method | — | JTAG / Passive Serial / FPP |