EP3SL50F484I4N vs EP3SL50F484I3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL50F484I4N sa pamamagitan ng Intel at EP3SL50F484I3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3SL50F484I4N | EP3SL50F484I3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Huling Pagbili |
| Series | Stratix III L | — |
| Family | Stratix III | Stratix III L |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 47,500 | 47,500 |
| LABs (Logic Array Blocks) | 1,900 | — |
| Total Memory Bits | 2,184,192 | — |
| User I/Os | 296 | — |
| Packhaging | 484-ball FC-FBGA | 484-ball FBGA (FC-FBGA, 23x23 mm, 1.0 mm pitch) |
| Temperature na Operasyon | -40C to +100C (Industrial) | — |
| Speed Grade | 4 | — |
| Core Voltage | 1.1 V (typical) | 0.9 V / 1.1 V |
| Process Technology | 65 nm | 65 nm CMOS |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (SMT) |
| Lead-Free / RoHS | Lead Free / RoHS Compliant | Lead Free / Compliant |
| Internal Clock Frequency (max) | 450 MHz (family typical) | — |
| Logic Array Blocks (LABs) | — | 1,900 |
| Embedded Memory | — | 2,184,192 bits (2.1 Mbit) |
| Embedded 18x18 Multipliers | — | 218 |
| Maximum User I/O | — | 296 |
| Maximum Core Frequency | — | 500 MHz |
| Temperature ng Junction na Operasyon | — | -40C to +100C (Industrial) |
| Level ng MSL | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Programming Tool | — | Quartus II (legacy) |