EP3SL50F780C4N vs EP3SL50F780C4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL50F780C4N sa pamamagitan ng Intel at EP3SL50F780C4 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3SL50F780C4N | EP3SL50F780C4 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Family | Stratix III L | Stratix III L |
| Series | EP3SL50 | — |
| Logic Elements (LEs) | 47,500 | — |
| Number of LABs / CLBs | 1,900 | — |
| Total RAM Bits | 2,184,192 (273 KB) | — |
| Number of User I/Os | 488 | — |
| Number of GPIO | 488 | — |
| Packhaging | 780-BBGA, FCBGA (FBGA-780) | 780-ball FC-FBGA |
| Process Technology | 65 nm CMOS | 65 nm |
| Speed Grade | -4 | C4 |
| Temperature na Operasyon | 0C to +85C (commercial) | 0C to +85C (Commercial) |
| Core Voltage Range | 0.86 V to 1.15 V | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead Free / RoHS | Lead free, RoHS compliant per distributor listing | — |
| Maximum Operating Frequency | 717 MHz (per family) | — |
| DSP Blocks | Hard DSP blocks (Stratix III family) | — |
| Memory Interface Support | DDR, DDR2, DDR3 (family feature) | — |
| Logic Elements | — | 47,500 |
| Embedded Memory | — | 2,184,192 bits |
| Logic Array Blocks (LABs) | — | 1,900 |
| User I/Os | — | 488 |
| Core Voltage | — | 1.1 V |
| Configuration Interface | — | JTAG / Serial |
| Design Tool | — | Quartus II |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |