EP3SL50F780I3N vs EP3SL50F780C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL50F780I3N sa pamamagitan ng Altera at EP3SL50F780C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP3SL50F780I3N - Stratix III L FPGA, 47.5K LE, FBGA-780 | Intel
EP3SL50F780I3N ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP3SL50F780I3N | EP3SL50F780C4N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Manufacturer | Altera (Intel Programmable Solutions Group) | — |
| Series | Stratix III L | EP3SL50 |
| Logic Elements | 47,500 | — |
| Number of LABs | 1,900 | — |
| Embedded Memory Bits | 2,184,192 bits | — |
| Maximum User I/O | 488 | — |
| Operating Frequency (max) | 500 MHz | — |
| Process Technology | 65 nm CMOS | 65 nm CMOS |
| Core Supply Voltage | 1.1 V | — |
| Speed Grade | -3 | -4 |
| Packhaging | 780-ball FC-FBGA (Flip-Chip BGA) | 780-BBGA, FCBGA (FBGA-780) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40C to +100C (industrial) | 0C to +85C (commercial) |
| JTAG Support | IEEE Std 1149.1 Boundary-Scan | — |
| Tindminan RoHS | Compliant (LEAD FREE) | — |
| Configuration Method | JTAG / Serial / Passive / Active | — |
| Family | — | Stratix III L |
| Logic Elements (LEs) | — | 47,500 |
| Number of LABs / CLBs | — | 1,900 |
| Total RAM Bits | — | 2,184,192 (273 KB) |
| Number of User I/Os | — | 488 |
| Number of GPIO | — | 488 |
| Core Voltage Range | — | 0.86 V to 1.15 V |
| Lead Free / RoHS | — | Lead free, RoHS compliant per distributor listing |
| Maximum Operating Frequency | — | 717 MHz (per family) |
| DSP Blocks | — | Hard DSP blocks (Stratix III family) |
| Memory Interface Support | — | DDR, DDR2, DDR3 (family feature) |