EP4CE55F29I8N vs EP4CE55F29I8LN Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP4CE55F29I8N sa pamamagitan ng Altera at EP4CE55F29I8LN sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP4CE55F29I8N | EP4CE55F29I8LN |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Cyclone IV E | — |
| Logic Elements (LEs) | 55,856 | 55,856 |
| Embedded Memory (bits) | 2,396,160 | — |
| Embedded 18x18 Multipliers | 374 | — |
| General-Purpose PLLs | 4 | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count for F29 package] | 374 |
| Packhaging | 780-ball FBGA (F29, 29x29 mm) | 780-ball FBGA (F29) |
| Process Technology | 60 nm low-power CMOS | 60 nm TSMC low-power |
| Temperature na Operasyon | -40C to +100C (Industrial grade, suffix I) | -40C to +85C (Industrial) |
| Supply Voltage Core | 1.0 V (typical, VCCINT) | — |
| I/O Bank Supply Voltages | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V | — |
| Configuration Modes | Active Serial (AS), Passive Serial (PS), JTAG, Fast Passive Parallel (FPP) | JTAG, AS, PS, FPP |
| External Memory Interfaces | DDR, DDR2, SDR, QDRII, QDRII+ SRAM | — |
| Differential I/O Standards | LVDS, RSDS, mini-LVDS, LVPECL (receive) | — |
| Tindminan RoHS | Compliant | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Family | — | Cyclone IV E |
| Device Model | — | EP4CE55 |
| Logic Array Blocks (LABs) | — | 3,135 |
| Total Embedded Memory Bits | — | 2,396,160 bits |
| Embedded Memory (M9K blocks) | — | 260 blocks |
| 18x18 Hardware Multipliers | — | 374 |
| PLLs | — | 4 |
| Core Voltage | — | 1.2 V |
| Ball Pitch | — | 1.0 mm |
| Lead-Free / RoHS | — | Yes (per OPN suffix N) |
| Supported I/O Standards | — | LVTTL, LVCMOS, LVDS, SSTL, HSTL |