EP4CGX150DF31C7N vs EP4CGX150DF31C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP4CGX150DF31C7N sa pamamagitan ng Intel at EP4CGX150DF31C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP4CGX150DF31C7 - 149760 Cells Cyclone IV GX FPGA, 896-FBGA | Intel
EP4CGX150DF31C7 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP4CGX150DF31C7N | EP4CGX150DF31C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Cyclone IV GX | — |
| Device Logic Elements | 149,760 | — |
| Total Memory Bits | 6,635,520 bit | — |
| Number of LABs/CLBs | 9,360 | — |
| Number of Logic Cells | 149,760 | — |
| Maximum User I/O | 475 | — |
| Supply Voltage Core | 1.2 V | — |
| Process Technology | 60 nm | 60 nm |
| Number of Transceivers | 8 (600 Mbps to 3.125 Gbps) | — |
| Embedded Multipliers | 18 x 18 hardware multipliers | — |
| Total RAM Bits | 6,635,520 bit (720 Kbit distributed + block RAM) | — |
| Number of PLLs | Up to 6 (5 outputs each) | — |
| Temperature na Operasyon | 0C to +85C (Commercial, C7 speed grade) | 0C to +85C (commercial) |
| Packhaging | 896-FBGA (FineLine BGA), 31 mm, F31 | 896-FBGA |
| Uri ng Pagpapasok | Surface Mount | — |
| Configuration | SRAM-based, JTAG/Active Serial/Active Parallel | JTAG / Active Serial / Passive Parallel |
| Speed Grade | 7 (C7, commercial) | C7 (commercial) |
| Tindminan RoHS | Compliant | Compliant |
| Device Family | — | Cyclone IV GX |
| Logic Elements | — | 149760 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Embedded Memory (Bits) | — | 6635520 |
| Embedded Memory Blocks (M9K) | — | [DATA_NEEDED: M9K block count] |
| User I/O Pins | — | 475 |
| Transceiver Channels | — | Up to 8 |
| Transceiver Data Rate (Max) | — | 3.125 Gbps |
| 18x18 Hardware Multipliers | — | 360 |
| PLLs | — | 4 |
| Global Clock Networks | — | [DATA_NEEDED: global clock count] |
| Core Voltage | — | 1.2 V |
| Pin/Package Count | — | 672 balls / 896-BGA pad pattern |
| Bitstream Encryption | — | AES-256 supported |