EP4SGX360FH29I4N vs EP4SGX360FH29I3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP4SGX360FH29I4N sa pamamagitan ng Intel at EP4SGX360FH29I3N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP4SGX360FH29I4N - Stratix IV GX FPGA 360K LE, 780-BGA | Intel
EP4SGX360FH29I4N ⚠ Huling PagbiliAltera
EP4SGX360FH29I3N - Stratix IV GX FPGA, 353600 Cells, 780-FCBGA | Altera
EP4SGX360FH29I3N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP4SGX360FH29I4N | EP4SGX360FH29I3N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Huling Pagbili |
| Family | Stratix IV GX | Stratix IV GX |
| Series | EP4SGX360 | — |
| Logic Elements | 353,600 | 353,600 |
| Logic Array Blocks (LABs) | 14,144 | — |
| Embedded Memory | 23,105,536 bits | 23,105,536 bits (22.0 Mbit) |
| User I/Os | 289 | 289 |
| Number of Pins/balls | 780 | — |
| Packhaging | 780-BGA, FCBGA (FH29) | 780-ball FCBGA (FH29), flip-chip |
| Ball Pitch | 1.0 mm | — |
| Temperature na Operasyon | -40C to +100C (industrial, I4 grade) | -40C to +100C (Industrial) |
| Volte ng Pagbibigay | [DATA_NEEDED: core voltage and transceiver supply] | — |
| Transceiver Count | [DATA_NEEDED: exact transceiver count for FH29 package option] | — |
| Max Transceiver Data Rate | 8.5 Gbps | — |
| Embedded Multipliers (18x18) | 36 (per family spec; device-specific value [DATA_NEEDED]) | — |
| PLLs | 4 | — |
| Process Node | 40nm TSMC | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | Compliant | Compliant |
| Configuration Mode | JTAG / Active Serial / Passive Parallel | — |
| Hard PCIe IP | PCIe Gen1/Gen2 hard IP blocks | — |
| Adaptive Logic Modules (ALMs) | — | 14,144 |
| Embedded 18x18 Multipliers | — | 1,320 |
| Transceiver Channels | — | 24 (up to 8.5 Gbps) |
| Process Technology | — | 40 nm |
| Core Voltage | — | 0.9 V |
| Hard Memory Controller | — | Yes (DDR2/DDR3) |
| PCIe Hard IP | — | Yes (Gen1/Gen2 x1/x2/x4) |
| Partial Reconfiguration | — | Supported |
| Configuration Scheme | — | Passive Serial, Fast Passive Parallel, JTAG |