EP610DC-15 vs EP610DC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-15 sa pamamagitan ng Altera at EP610DC-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC-15 | EP610DC-20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | — |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | 4 |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | 22 ns |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Temperature na Operasyon | 0C to 70C (commercial) | 0 °C to 70 °C (commercial) |
| Packhaging | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Uri ng Pagpapasok | Through-Hole | Through-hole |
| Programming Method | JEDEC fuse map, UV erasure | UV erasure + parallel programmer |
| Technology | CMOS | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Product Type | — | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Family | — | Classic EP610 |
| Logic Macrocells | — | 16 |
| I/O Pins | — | 16 (bidirectional) |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Process Technology | — | CMOS, UV-erasable floating gate |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |