EP610DC-15 vs EP610ILC-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-15 sa pamamagitan ng Altera at EP610ILC-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC-15 | EP610ILC-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | PAL-type with macrocells |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | 4 |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | — |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Temperature na Operasyon | 0C to 70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Packhaging | 24-pin Ceramic DIP (CDIP-24) with UV window | PLCC-28 (plastic J-lead chip carrier) |
| Uri ng Pagpapasok | Through-Hole | Surface Mount (PLCC socket or solder) |
| Programming Method | JEDEC fuse map, UV erasure | — |
| Technology | CMOS | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | Classic EPLD |
| Product Type | — | UV-Erasable / OTP PLD |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| I/O Pins | — | 16 |
| Volte ng Pagbibigay | — | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |