EP610DC-20 vs EP610DC15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-20 sa pamamagitan ng Intel at EP610DC15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC-20 | EP610DC15 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Classic EP610 | EP610 Classic EPLD |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 (bidirectional) | — |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | 15 ns |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| Temperature na Operasyon | 0 °C to 70 °C (commercial) | 0C to +70C |
| Packhaging | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CDIP (Ceramic DIP, windowed) |
| Programming Method | UV erasure + parallel programmer | — |
| Process Technology | CMOS, UV-erasable floating gate | — |
| Uri ng Pagpapasok | Through-hole | Through-Hole |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Macrocells | — | 16 |
| Architecture | — | PAL-type |
| Maximum Clock Frequency (fMAX) | — | 71.4 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Total Inputs | — | 20 |
| I/O Lines | — | 16 |
| Product Terms | — | 160 |
| Technology | — | CMOS |
| Reprogrammability | — | Yes (UV erasable via windowed package) |