EP610DC-25 vs EP610DC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-25 sa pamamagitan ng Rochester Electronics at EP610DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP610DC-25 | EP610DC-35 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Family | Altera Classic EPLD | Altera Classic EP610 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Equivalent Gates | 300 | — |
| Maximum Propagation Delay (tPD) | 25 ns | — |
| Pipelined Data Rate | Up to 100 MHz | up to 100 MHz |
| Number of I/O Pins | 22 | — |
| Number of Dedicated Inputs | 4 | — |
| Total Pin Count | 24 | — |
| Packhaging | 24-pin CDIP (Ceramic DIP, through-hole) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Uri ng Pagpapasok | Through Hole | Through-Hole (DIP) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Temperature na Operasyon | 0 C to +70 C | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Technology | CMOS EPROM (UV-erasable) | — |
| Programming Method | JEDEC fuse-map / UV-erase | — |
| Speed Grade Suffix | -25 (25 ns tPD) | — |
| Device Type | — | CPLD - Classic EPLD |
| Usable Gates | — | 300 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |
| Tindminan RoHS | — | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |