EP610DI-25 vs EP610IDC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DI-25 sa pamamagitan ng Intel at EP610IDC-15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DI-25 | EP610IDC-15 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Part Family | Classic EPLD | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 25 ns | 15 ns |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) | — |
| I/O Pins | 16 (bidirectional) | 24 (per package; macrocell-programmable) |
| Dedicated Inputs | 4 | — |
| Total User I/O | 20 | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V (5 V nominal) |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 | — |
| Bilang ng Pin | 24 | — |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-hole |
| Temperature na Operasyon | Industrial (per "I" suffix) | 0C to +70C (commercial) |
| Speed Grade Suffix | 25 = 25 ns | — |
| Compliance | RoHS status unknown (legacy 1990s part) | — |
| Device Family | — | Altera Classic EPLD |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 66 MHz |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Packhaging | — | 24-pin CerDIP (ceramic DIP) |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |