EP610IDC-10 vs EP610DC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610IDC-10 sa pamamagitan ng Intel at EP610DC-25 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP610IDC-10 | EP610DC-25 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Device Family | Altera Classic EPLD | — |
| Logic Capacity | 300 usable gates | — |
| Macrocell Count | 16 macrocells | — |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | — |
| Maximum Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Compatibility | 100% TTL emulation | — |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS EPROM (UV-erasable) |
| Package Type | 24-pin Ceramic DIP (CDIP) | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 20 | — |
| Hanay ng Temperature na Operasyon | 0 °C to +70 °C (commercial) | — |
| Programmable Interconnect | Yes (on-chip) | — |
| In-System Programmability | Yes (via MAX+PLUS II) | — |
| Boundary-Scan Test | Yes (per device documentation) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status of CDIP-10 variant] | — |
| Uri ng Pagpapasok | Through-hole | Through Hole |
| Family | — | Altera Classic EPLD |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Packhaging | — | 24-pin CDIP (Ceramic DIP, through-hole) |
| Temperature na Operasyon | — | 0 C to +70 C |
| Programming Method | — | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | — | -25 (25 ns tPD) |