EP610PC-15 vs EP610DC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610PC-15 sa pamamagitan ng Altera at EP610DC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610PC-15 | EP610DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 300 gates | — |
| Macrocells | 16 | 16 |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V |
| Technology | CMOS | CMOS |
| Architecture | PAL-type, sum-of-products AND/OR array | UV-erasable CMOS PAL-type |
| TTL Emulation | 100% TTL compatible | — |
| Packhaging | PDIP-24 (plastic DIP, 24-pin) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Bilang ng Pin | 24 pins | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0C to 70C (commercial) |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Development Tool | Altera MAX+PLUS II | — |
| Logic Test Circuitry | On-board for AC/DC verification | — |
| Product Family | — | Classic EPLD (EP610) |
| Logic Expanders | — | 4 |
| Dedicated Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Propagation Delay (tPD) | — | 15 ns (speed grade -15) |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| Programming Method | — | JEDEC fuse map, UV erasure |