EP610PC-25 vs EP610PC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610PC-25 sa pamamagitan ng Altera at EP610PC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610PC-25 | EP610PC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Family | Classic EPLD (EP610 series) | — |
| Macro Cells | 16 | — |
| Usable Gates | 300 | 300 gates |
| Propagation Delay (tpd) | 25 ns | — |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Technology | CMOS, EPROM (UV-erasable) | CMOS |
| Device Type | OT PLD, PAL-type, CMOS | EPLD (Erasable Programmable Logic Device) |
| Dedicated Inputs | 4 | — |
| I/O Pins | 20 (bidirectional, JTAG-programmable OE per macrocell) | — |
| Packhaging | PDIP-24 (0.3 inch, through-hole) | PDIP-24 (plastic DIP, 24-pin) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature range] |
| Programming Method | EPROM (UV-erasable), via Altera programming hardware | — |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole (DIP) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Family | — | Classic EPLD |
| Macrocells | — | 16 |
| Logic Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Maximum Counter Frequency | — | 100 MHz (per family datasheet) |
| Pipelined Data Rate | — | Up to 100 MHz |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Architecture | — | PAL-type, sum-of-products AND/OR array |
| TTL Emulation | — | 100% TTL compatible |
| Bilang ng Pin | — | 24 pins |
| Development Tool | — | Altera MAX+PLUS II |
| Logic Test Circuitry | — | On-board for AC/DC verification |