EP910DC-15 vs EP910IDC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DC-15 sa pamamagitan ng Altera at EP910IDC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910DC-15 | EP910IDC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD |
| Device Density | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Logic Elements | [DATA_NEEDED: exact LE count] | — |
| Dedicated Inputs | 12 | 10 |
| Bidirectional I/O Pins | 12 | — |
| Flip-Flops | 10 | 48 |
| Product Terms per Macrocells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Speed Grade | 15 | — |
| Supply Voltage (VCC) | 5 V (typical) | 5 V |
| Temperature na Operasyon | 0C to +70C (commercial) | — |
| Technology | CMOS EPROM, UV-erasable | — |
| Packhaging | 24-pin ceramic DIP (DC) | 40-pin CDIP (Ceramic DIP, through-hole) |
| Uri ng Pagpapasok | Through-Hole | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: not explicitly stated in verified data] | non_compliant (ceramic DIP contains lead) |
| Manufacturer | — | Altera (now Intel PSG) |
| Equivalent Gates | — | 450 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| I/O Pins | — | 24 |
| Programming Technology | — | EPROM (UV-erasable) |