EP910DM883B vs EP910DC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DM883B sa pamamagitan ng Altera at EP910DC-30 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910DM883B | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Manufacturer | Altera (now part of Intel) | — |
| Family | Classic EPLD - EP910 Series | Classic EPLD (EP910 series) |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type AND-OR-NOT, CMOS | PAL-type AND-OR sum-of-products, CMOS |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Outputs | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns (typical) | 30 ns (max) |
| Maksimum na Taktiko ng Oras | 25 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Programming Voltage (VPP) | 12.5 V (UV-erase window) | — |
| Temperature na Operasyon | -55 °C to +125 °C (military) | 0C to +70C (commercial) |
| Packhaging | CDIP-40 (Ceramic DIP, 40-pin) | DIP-40 (through-hole, 600 mil) |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole |
| MIL Processing | MIL-STD-883B Class B | — |
| Configuration Memory | UV-erasable EPROM | — |
| Logic Elements | Combinational + Registered | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Gate Count | — | 900 usable gates |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Dedicated Inputs | — | 36 |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Volte ng Pagbibigay | — | 5 V |
| Process Technology | — | CMOS |
| Programming Method | — | UV-Erasable / OTP |