EP910DM883B vs EP910DI-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DM883B sa pamamagitan ng Altera at EP910DI-30 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 NrndPagsanggunian na paghahambing
| Parametro | EP910DM883B | EP910DI-30 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Manufacturer | Altera (now part of Intel) | — |
| Family | Classic EPLD - EP910 Series | Classic EPLD (Altera EP910 series) |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type AND-OR-NOT, CMOS | — |
| Macrocells | 24 | — |
| Inputs | 36 | — |
| Outputs | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns (typical) | — |
| Maksimum na Taktiko ng Oras | 25 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| Programming Voltage (VPP) | 12.5 V (UV-erase window) | — |
| Temperature na Operasyon | -55 °C to +125 °C (military) | -40C to +85C (industrial) |
| Packhaging | CDIP-40 (Ceramic DIP, 40-pin) | CDIP-40 (ceramic DIP, 40-pin with UV window) |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole (DIP) |
| MIL Processing | MIL-STD-883B Class B | — |
| Configuration Memory | UV-erasable EPROM | — |
| Logic Elements | Combinational + Registered | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Product Type | — | UV-Erasable Programmable Logic Device (EPLD) |
| Macrocell Count | — | 24 |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Toggle Frequency (fmax) | — | 62 MHz |
| Technology | — | CMOS, UV-erasable EPROM |
| Dedicated Inputs | — | 10 |
| Dedicated I/O Pins | — | 12 (12 input + 12 output) |
| Output Enable Pins | — | 2 |
| Bilang ng Pin | — | 40 |
| Programmable Logic Element | — | JEDEC fuse map (3rd-party programmer) |
| Manufacturer (Original) | — | Altera (now Intel PSG) |
| Current Distributor / Authorized Aftermarket | — | Rochester Electronics, LLC |