EP910ILC-15 vs EP910DI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-15 sa pamamagitan ng Intel at EP910DI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910ILC-15 | EP910DI-35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Aktibo |
| Family | Classic EPLD | Altera Classic EPLD |
| Series | EP910 | — |
| Logic Gates | 450 | — |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 15 ns | 35 ns |
| Maximum Operating Frequency | 83.33 MHz | — |
| Volte ng Pagbibigay | 5 V | — |
| Uri ng Memory | EPROM (UV-erasable) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Packhaging | 44-pin PLCC (J-lead) | CDIP-40 (Ceramic DIP with UV window) |
| Uri ng Pagpapasok | Surface Mount (SMT) | Through-Hole |
| Propagation Class | -15 speed grade | — |
| Storage Condition | Dry cabinet, humidity-controlled | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Maximum Toggle Frequency (fCNT) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Supply Current (ICC) | — | 40 mA typical |
| Dedicated Inputs | — | 10 |
| Bidirectional I/O Pins | — | 20 |
| Total Pins | — | 40 |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | EPROM programmer + JEDEC fuse map |
| Erasure Method | — | UV light through quartz window |
| Logic Family | — | PAL-type AND/OR array with D flip-flops |
| Manufacturer | — | Original Altera; long-term authorized by Rochester Electronics, LLC |