EP910ILC-15 vs EP910ILC-50 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-15 sa pamamagitan ng Intel at EP910ILC-50 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910ILC-15 | EP910ILC-50 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Series | EP910 | — |
| Logic Gates | 450 | — |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | 24 |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 83.33 MHz | — |
| Volte ng Pagbibigay | 5 V | — |
| Uri ng Memory | EPROM (UV-erasable) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Packhaging | 44-pin PLCC (J-lead) | PLCC-44 (J-lead) |
| Uri ng Pagpapasok | Surface Mount (SMT) | Surface Mount (socket-compatible) |
| Propagation Class | -15 speed grade | — |
| Storage Condition | Dry cabinet, humidity-controlled | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Usable Gates | — | 900 (typical) |
| Maximum Frequency | — | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | — | 50 ns |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Dedicated Input Pins | — | 12 |
| Technology | — | CMOS EPROM, UV-erasable |
| Programming Cycles | — | 100 (minimum) |
| Boundary Scan | — | IEEE 1149.1 JTAG (selected speed grades) |