EP910ILC-15N vs EP910ILC-50 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-15N sa pamamagitan ng Altera at EP910ILC-50 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N ObsoletePagsanggunian na paghahambing
| Parametro | EP910ILC-15N | EP910ILC-50 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic | Altera Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 | — |
| Macro Cells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 66.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| User I/O Pins | 36 | 24 |
| Dedicated Input Pins | 16 | 12 |
| Packhaging | PLCC-44 (J-lead, surface mount) | PLCC-44 (J-lead) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (socket-compatible) |
| Temperature na Operasyon | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Process Technology | CMOS EPROM (one-time programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Programming | EPROM / JTAG (Classic EP-series) | — |
| Macrocells | — | 24 |
| Usable Gates | — | 900 (typical) |
| Maximum Frequency | — | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | — | 50 ns |
| Technology | — | CMOS EPROM, UV-erasable |
| Programming Cycles | — | 100 (minimum) |
| Boundary Scan | — | IEEE 1149.1 JTAG (selected speed grades) |