EP910LC-30 vs EP910DC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-30 sa pamamagitan ng Altera at EP910DC-30 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LC-30 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocell Count | 24 | — |
| Propagation Delay (tPD) | 30 ns (max) | 30 ns (max) |
| Maximum Toggle Frequency | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal, TTL) | — |
| Process Technology | CMOS (EPROM-based) | CMOS |
| Package Type | PDIP-40 (Plastic DIP, through-hole) | — |
| Operating Temperature Grade | Commercial (0C to +70C) | — |
| I/O Pin Count | 24 | — |
| Dedicated Input Pins | 36 (including I/O) | — |
| Product Terms per Macrocell | Up to 16 | — |
| Programming Technology | UV-erasable EPROM cell | — |
| Development Tool | Altera MAX+PLUS II | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Family | — | Classic EPLD (EP910 series) |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Macrocells | — | 24 |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Dedicated Inputs | — | 36 |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Volte ng Pagbibigay | — | 5 V |
| Programming Method | — | UV-Erasable / OTP |
| Packhaging | — | DIP-40 (through-hole, 600 mil) |
| Temperature na Operasyon | — | 0C to +70C (commercial) |
| Uri ng Pagpapasok | — | Through-Hole |