EP910LC-35T vs EP910LI-35T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-35T sa pamamagitan ng Altera at EP910LI-35T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LC-35T | EP910LI-35T |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Family | Classic EPLD (EP910) | Classic EPLD (EP910) |
| Logic Capacity | 450 usable gates | — |
| Macrocells | 24 | — |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Operating Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (4.75 V to 5.25 V) |
| User I/O Pins | 36 | — |
| Packhaging | PLCC-44 (J-lead) | 44-pin PLCC (JEDEC) |
| Process Technology | CMOS (EPROM-based) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | -40C to +85C (industrial, 'I' suffix) |
| Erasure Method | UV-erasable window (ceramic package) / OTP (plastic) | — |
| Programming | Altera programming hardware + MAX+PLUS II | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket or solder) | Surface Mount / Socket |
| Level ng MSL | MSL 3 (168 hours) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status not in verified data] | [DATA_NEEDED: RoHS compliance] |
| Logic Elements | — | 24 macrocells |
| Usable Gates | — | 450 |
| Maximum Toggle Frequency (fMAX) | — | 28.6 MHz |
| Technology | — | CMOS, EPROM-based |
| Programming Method | — | EPROM (UV-erasable for windowed versions) |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Number of I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |