EP910LC44-35 vs EP910LC44-40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC44-35 sa pamamagitan ng Intel at EP910LC44-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LC44-35 | EP910LC44-40 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Classic EPLD (OT sub-family) | Altera Classic EPLD |
| Architecture | PAL-type AND/OR array | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns (max) | 40 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Total Inputs | 36 | 36 |
| I/O Pins | 24 | 24 (bidirectional) |
| Global Clocks | 2 | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V (nominal) |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Packhaging | 44-pin PLCC (J-leaded) | 44-pin PLCC (Plastic Leaded Chip Carrier) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | CMOS | — |
| Programmability | UV-erasable (windowed ceramic) | — |
| Product Terms (Total) | — | 240 |
| Dedicated Inputs | — | 12 |
| Global Clock Inputs | — | 2 |
| Technology | — | CMOS, UV-erasable EPROM |
| Logic Compatibility | — | TTL-compatible I/O |
| Programming Method | — | JEDEC file via LP6/MP9 or compatible programmer |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance] |