EP910LI-12 vs EP910LI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-12 sa pamamagitan ng Altera at EP910LI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-12 | EP910LI-35 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 900 |
| Propagation Delay (tPD) | 12 ns | — |
| Maximum Frequency (fMAX) | 76.9 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V typical) | — |
| I/O Pins | 24 | — |
| Inputs (with input registers) | 36 | — |
| Packhaging | 28-PLCC (windowed ceramic, J-Lead) | 44-pin PLCC (J-lead) |
| Temperature na Operasyon | -40C to +85C (industrial) | -40 °C to +85 °C (Industrial) |
| Process Technology | 1.0-micron CMOS EPROM | CMOS EPROM |
| Power Dissipation (typical) | 200 mW at 5 V | — |
| Programming Method | UV-erasable via windowed package | — |
| Logic Compatibility | TTL-compatible I/O | — |
| Tindminan RoHS | non_compliant (ceramic windowed package) | — |
| Family | — | Altera Classic EPLD |
| Device Series | — | EP910 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| Volte ng Pagbibigay | — | 5 V (4.75 V to 5.25 V) |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| Uri ng Pagpapasok | — | Surface Mount |
| Lead Pitch | — | 1.27 mm |