EP910LI-20T vs EP910LC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-20T sa pamamagitan ng Altera at EP910LC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-20T | EP910LC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD (Altera) | — |
| Macrocells | 24 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 20 | — |
| Propagation Delay (tPD) | 20 ns | 30 ns (max) |
| Maximum Frequency (fMAX) | 95 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (nominal, TTL) |
| Programming Technology | CMOS EPROM (UV-erasable) | UV-erasable EPROM cell |
| Programming Voltage | 21 V | — |
| Packhaging | CDIP-20 (ceramic DIP, through-hole) | — |
| Speed Grade | -20 | — |
| Temperature na Operasyon | -40 C to +85 C (industrial) | — |
| Uri ng Pagpapasok | Through-hole | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Level ng MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | — | 24 |
| Maximum Toggle Frequency | — | 62 MHz |
| Process Technology | — | CMOS (EPROM-based) |
| Package Type | — | PDIP-40 (Plastic DIP, through-hole) |
| Operating Temperature Grade | — | Commercial (0C to +70C) |
| I/O Pin Count | — | 24 |
| Dedicated Input Pins | — | 36 (including I/O) |
| Product Terms per Macrocell | — | Up to 16 |
| Development Tool | — | Altera MAX+PLUS II |