EP910LI-35 vs EP910LI-35T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-35 sa pamamagitan ng Altera at EP910LI-35T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-35 | EP910LI-35T |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Family | Altera Classic EPLD | Classic EPLD (EP910) |
| Device Series | EP910 | — |
| Usable Gates | 900 | 450 |
| Macrocells | 24 | — |
| Maximum User I/O Pins | 38 | — |
| Propagation Delay (t_PD) | 35 ns | — |
| Maximum Counter Frequency (f_CNT) | 76.9 MHz | — |
| Volte ng Pagbibigay | 5 V (4.75 V to 5.25 V) | — |
| Temperature na Operasyon | -40 °C to +85 °C (Industrial) | -40C to +85C (industrial, 'I' suffix) |
| Packhaging | 44-pin PLCC (J-lead) | 44-pin PLCC (JEDEC) |
| Process Technology | CMOS EPROM | — |
| Programming Technology | EPROM (UV-erasable) | — |
| Erase/Program Cycles | ≥100 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount / Socket |
| Lead Pitch | 1.27 mm | — |
| Logic Elements | — | 24 macrocells |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency (fMAX) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Technology | — | CMOS, EPROM-based |
| Programming Method | — | EPROM (UV-erasable for windowed versions) |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Number of I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |